DS3106LN+【PDF 27/92 页】IC TIMING LINE CARD 64-LQFP

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DS3106

Table 7-17. OC3 Default Frequency Configuration

O3F[2:0]

SONSDH

FREQUENCY

(MHz)

O6F[2:0]

=001

OCR2.

OFREQ3

APLL

SRC

000

0000

—

001

8.192

FALSE

1101

6.176

1101

001

8.192

TRUE

0111

12.352

0111

010

68.736

1111

010

22.368

1110

011*

19.44

0110

100

25.92

0111

101

38.88

1000

110

51.84

1001

111

77.76

1010

*Occurs when O3F[2:0] are left unconnected.

7.8.2.5 FSYNC and MFSYNC Configuration

The FSYNC output is enabled by setting FSEN = 1 in the OCR4 register, while the MFSYNC output is enabled by

setting MFSEN = 1 in OCR4. When disabled, these pins are driven low.

When 8KPUL = 0 in FSCR1, FSYNC is configured as an 8kHz clock with 50% duty cycle. When 8KPUL = 1,

FSYNC is an 8kHz frame sync that pulses low once every 125

s with pulse width equal to one cycle of output

clock OC3. When 8KINV = 1 in FSCR1, the clock or pulse polarity of FSYNC is inverted.

When 2KPUL = 0 in FSCR1, MFSYNC is configured as an 2kHz clock with 50% duty cycle. When 2KPUL = 1,

MFSYNC is a 2kHz frame sync that pulses low once every 500

s with pulse width equal to one cycle of output

clock OC3. When 2KINV = 1 in FSCR1, the clock or pulse polarity f MFSYNC is inverted.

If either 8KPUL = 1 or 2KPUL = 1, output clock OC3 must be generated from the T0 DPLL and must be configured

for a frequency of 1.544MHz or higher or the FSYNC/MFSYNC pulses may not be generated correctly. Figure 7-3

shows how the 8KPUL and 8KINV control bits affect the FSYNC output. The 2KPUL and 2KINV bits have an

identical effect on MFSYNC.

Figure 7-3. FSYNC 8kHz Options

OC3 OUTPUT CLOCK

FSYNC, 8KPUL=0, 8KINV=0

FSYNC, 8KPUL=0, 8KINV=1

FSYNC, 8KPUL=1, 8KINV=0

FSYNC, 8KPUL=1, 8KINV=1

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